



#include	"main.h"


void LPSPI1_init_master(void) 
{
  PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
  PORTB->PCR[14]|=PORT_PCR_MUX(3); /* Port B14: MUX = ALT3, LPSPI1_SCK */
  PORTB->PCR[15]|=PORT_PCR_MUX(3); /* Port B15: MUX = ALT3, LPSPI1_SIN */
  PORTB->PCR[16]|=PORT_PCR_MUX(3); /* Port B16: MUX = ALT3, LPSPI1_SOUT */
  PORTB->PCR[17]|=PORT_PCR_MUX(3); /* Port B17: MUX = ALT3, LPSPI1_PCS3 */
	

  PCC->PCCn[PCC_LPSPI1_INDEX] &= ~PCC_PCCn_CGC_MASK; 			 	/* Disable clocks to modify PCS ( default) */
  PCC->PCCn[PCC_LPSPI1_INDEX] |= PCC_PCCn_PCS(6)						/* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
                              |  PCC_PCCn_CGC_MASK;   			/* Enable clock for LPSPI regs */

  LPSPI1->CR    = 0x00000000;   /* Disable module for configuration */
  LPSPI1->IER   = 0x00000000;   /* Interrupts not used */
  LPSPI1->DER   = 0x00000000;   /* DMA not used */
  LPSPI1->CFGR0 = 0x00000000;   /* Defaults: */
                                /* RDM0=0: rec'd data to FIFO as normal */
                                /* CIRFIFO=0; Circular FIFO is disabled */
                                /* HRSEL, HRPOL, HREN=0: Host request disabled */
  LPSPI1->CFGR1 = 0x00000005;   /* Configurations: master mode*/
                                /* PCSCFG=0: PCS[3:2] are enabled */
                                /* OUTCFG=0: Output data retains last value when CS negated */
                                /* PINCFG=0: SIN is input, SOUT is output */
                                /* MATCFG=0: Match disabled */
                                /* PCSPOL=0: PCS is active low */
                                /* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
                                /* AUTOPCS=0: does not apply for master mode */
                                /* SAMPLE=0: input data sampled on SCK edge */
                                /* MASTER=1: Master mode */
  LPSPI1->TCR   = 0x13200007;   /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc*/
                                /* CPOL=0: SCK inactive state is low */
                                /* CPHA=1: Change data on SCK lead'g, capture on trail'g edge*/
                                /* PRESCALE=2: Functional clock divided by 2**2 = 4 */
                                /* PCS=3: Transfer using PCS3 */
                                /* LSBF=0: Data is transfered MSB first */
                                /* BYSW=0: Byte swap disabled */
                                /* CONT, CONTC=0: Continuous transfer disabled */
                                /* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
                                /* TXMSK=0: Normal transfer: data loaded from tx FIFO */
                                /* WIDTH=0: Single bit transfer */
                                /* FRAMESZ=15: # bits in frame = 15+1=16 */
  LPSPI1->CCR   = 0x04090808;   /* Clock dividers based on prescaled func'l clk of 100 nsec */
                                /* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
                                /* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */
                                /* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
                                /* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */
  LPSPI1->FCR   = 0x00000000;   /* RXWATER=0: Rx flags set when Rx FIFO >0 */
                                /* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
  LPSPI1->CR    = 0x00000009;   /* Enable module for operation */
                                /* DBGEN=1: module enabled in debug mode */
                                /* DOZEN=0: module enabled in Doze mode */
                                /* RST=0: Master logic not reset */
                                /* MEN=1: Module is enabled */										
																
}

lpspi_tx_cmd_config_t Spi_TxCmdCfgSet = {
    .whichPcs = LPSPI_PCS3,										/* PCS=3: Transfer using PCS3 */
    .width = LPSPI_SINGLE_BIT_XFER,						/* WIDTH=0: Single bit transfer */
    .clkPhase = LPSPI_CLOCK_PHASE_1ST_EDGE,		/* CPHA=0: Change data on SCK lead'g, capture on trail'g edge*/
    .clkPolarity = LPSPI_SCK_ACTIVE_HIGH,			/* CPOL=0: SCK inactive state is HIGH */
    .lsbFirst = false,												/* LSBF=0: Data is transfered MSB first */
    .txMask 	= false,												/* TXMSK=0: Normal transfer: data loaded from tx FIFO */                          
    .rxMask		= false,												/* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
    .contTransfer = true,											/* CONT, CONTC=0: Continuous transfer disabled */
    .contCmd = false,													/* Master option to change cmd word within cont transfer. */
    .frameSize = 8,														/* FRAMESZ=7: # bits in frame = 7+1=8 */
    .preDiv    = 2,														/* PRESCALE=2: Functional clock divided by 2*2 = 4 */
    .byteSwap = false, 												/* BYSW=0: Byte swap disabled */
};




/********************************************************
**函数名：	BSW_LPSPI_INIT
**功能：		初始化 LPSPI_INIT
**输入参数	无
**返回值：	无
**注意：		
*********************************************************/
void BSW_LPSPI_INIT(void)
{
  PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
  PORTB->PCR[14]|=PORT_PCR_MUX(3); /* Port B14: MUX = ALT3, LPSPI1_SCK */
  PORTB->PCR[15]|=PORT_PCR_MUX(3); /* Port B15: MUX = ALT3, LPSPI1_SIN */
  PORTB->PCR[16]|=PORT_PCR_MUX(3); /* Port B16: MUX = ALT3, LPSPI1_SOUT */
  PORTB->PCR[17]|=PORT_PCR_MUX(3); /* Port B17: MUX = ALT3, LPSPI1_PCS3 */
	
	
  PCC->PCCn[PCC_LPSPI1_INDEX] &= ~PCC_PCCn_CGC_MASK; 			 	/* Disable clocks to modify PCS ( default) */
  PCC->PCCn[PCC_LPSPI1_INDEX] |= PCC_PCCn_PCS(6)						/* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
                              |  PCC_PCCn_CGC_MASK;   			/* Enable clock for LPSPI regs */


    LPSPI_Disable(LPSPI1);														/* Disable module for configuration */
    LPSPI_SetIntMode(LPSPI1,LPSPI_ALL_STATUS,false);	/* Interrupts not used */
    LPSPI_SetTxDmaCmd(LPSPI1,false);									/* DMA not used */
    LPSPI_SetRxDmaCmd(LPSPI1,false);									/* DMA not used */
    LPSPI_SetMasterSlaveMode(LPSPI1, LPSPI_MASTER);		/* Set for master mode */ 
    LPSPI_SetPinConfigMode(LPSPI1, LPSPI_SDI_IN_SDO_OUT, LPSPI_DATA_OUT_RETAINED, true);			
    LPSPI_ClearStatusFlag(LPSPI1,LPSPI_ALL_STATUS);

    LPSPI_SetBaudRateDivisor(LPSPI1,8);								/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */
    LPSPI_SetDelay(LPSPI1, LPSPI_SCK_TO_PCS, 4);			/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
    LPSPI_SetDelay(LPSPI1, LPSPI_PCS_TO_SCK,9);				/* PCSSCK=9: PCS to SCK delay = 9+1 = 10 (1 usec) */
    LPSPI_SetDelay(LPSPI1, LPSPI_BETWEEN_TRANSFER, 0);/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
    LPSPI_SetPcsPolarityMode(LPSPI1,LPSPI_PCS3 ,LPSPI_ACTIVE_LOW);
    LPSPI_SetSamplingPoint(LPSPI1, true);

    LPSPI_SetRxWatermarks(LPSPI1,0);									/* RXWATER=0: Rx flags set when Rx FIFO >0 */
    LPSPI_SetTxWatermarks(LPSPI1,0);									/* TXWATER=3: Tx flags set when Tx FIFO <= 3 */



    LPSPI_SetTxCommandReg(LPSPI1,&Spi_TxCmdCfgSet);

    LPSPI_Enable(LPSPI1);								/* Enable module for operation */
    													/* DBGEN=1: module enabled in debug mode */
    													/* DOZEN=0: module enabled in Doze mode */
    													/* RST=0: Master logic not reset */
    													/* MEN=1: Module is enabled */
}


uint16_t BSW_LPSPI_WirteRead(LPSPI_Type * base,uint16_t Send_Value) 
{
    uint16_t DataValue = 0;

    while(!(LPSPI_GetStatusFlag(base,LPSPI_TX_DATA_FLAG)));     /* Wait for Tx FIFO available */
    LPSPI_WriteData(base,Send_Value);                           /* Transmit data */
    LPSPI_ClearStatusFlag(base,LPSPI_TX_DATA_FLAG);             /* Clear TDF flag -- LPSPI1->SR |= LPSPI_SR_TDF_MASK; */

    while(!(LPSPI_GetStatusFlag(base,LPSPI_WORD_COMPLETE)));    /* Wait at least one RxFIFO entry */
    DataValue= LPSPI_ReadData(base);                            /* Read received data */
    LPSPI_ClearStatusFlag(base,LPSPI_WORD_COMPLETE);            /* Clear RDF flag */
    LPSPI_ClearStatusFlag(base,LPSPI_RX_DATA_FLAG);             /* Clear RDF flag */
    return DataValue;  
}


void LPSPI1_TxBuffer(uint8_t* Send_Buff,uint16_t *Rev_Buff)
{
    LPSPI_SetContCBit(LPSPI1);

    BSW_LPSPI_WirteRead(LPSPI1,0xC0);
    Rev_Buff[0] = BSW_LPSPI_WirteRead(LPSPI1,0x00);
    LPSPI_ClearContCBit(LPSPI1);
    Rev_Buff[1] = LPSPI_ReadDataBlocking(LPSPI1);
}


